View STB5600_77446.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

(R)
STB5600
GPS RF FRONT-END IC
s
s
s s s s s s
ONE CHIP SYSTEM TO INTERFACE ACTIVE ANTENNA TO ST20GP1 MICROCONTROLLER COMPLETE RECEIVER USING NOVEL DUAL CONVERSION ARCHITECTURE WITH SINGLE IF FILTER MINIMUM EXTERNAL COMPONENTS COMPATIBLE WITH GPS L1 SPS SIGNAL INTERNALLY STABILISED POWER RAILS CMOS OUTPUT LEVELS FROM 3.3 TO 5.9V SUPPLY VOLTAGE TQFP32 PACKAGE
TQFP32 MARKING: STB5600 TRACEAB. CODE ASSY CODE
DESCRIPTION The STB5600, using STMicroelectronics HSB2, High Speed Bipolar technology, implements a Global Positioning System RF front-end. The chip provides down conversion from the GPS (L1) signal at 1575 MHz via an IF of 20MHz to an output frequency of 4MHz suitable for ST20GP1 GPS processor. It uses a single external reference oscillator to generate both RF local oscillator signals and the processor reference clock.
PIN CONNECTION (top view)
August 1998
1/10
STB5600
FUNCTIONAL DESCRIPTION The STB5600 GPS front-end is fed with the signal from an active antenna, via a ceramic RF filter. The gain between the antenna element and the STB5600 is expected to be between 10dB and 35dB overall, made up of the antenna LNA gain, the feeder loss, connector loss, and the ceramic filter loss. In order to use an off-the-shelf ceramic filter, conventionally 50 Ohms single ended, a matching circuit is used. (see appendix A.1), which provides a 300 Ohm differential drive to the STB5600. A similar circuit can be used to feed the LO signal if using the recommended low-cost oscillator circuit (appendix A.3). Note that the STB5600 radio architecture and the oscillator described here are covered by various patents held by SGS-Thomson and by others. The use of the circuits described in this data-sheet for any other purpose may infringe such patents.
- RF SECTION
The differential input signal is amplified by the RF-Amp and mixed with the oscillator signal amplified from the LO+,LO- inputs to generate a balanced 20.46MHz IF signal. The LO buffer amplifier may be fed differential or single ended signals, at levels between -60dBm and -20dBm .
- IF SECTION
The 20MHz differential signal from the mixer is fed through an external LC filter to suppress undesirable signals and mixer products. The multi-stage high-sensitivity limiting amplifier is connected to a D-type latch clocked by an internally derived 16MHz clock.. The effect of sampling the 20MHz signal at 16MHz is to create a sub-sampling alias at 4MHz. This is fed to the output level-converters.
- DIVIDER SECTION
The 80MHz oscillator signal may be provided single-ended or differentially to the high impedance 80MHz+, 80MHz- inputs. Any unused inputs should be connected to GNDLOGIC via a 1nF capacitor. The 80MHz signal is amplified, then divided by 5 to create the 16.368MHz clock required by the ST20GP1 processor, also used to clock the output latch of the STB5600.
- OUTPUT SECTION
The output latch samples the 20.46MHz intermediate frequency at a 16.368MHz rate, performing the dual function of second downconversion and latching. The downconversion occurs by sub-sampling aliasing, such that the digital output represents a 4.096MHz centre frequency The output buffers perform level translation from the internal ECL levels to CMOS compatible outputs referred to external ground.
ABSOLUTE MAXIMUM RATINGS
Symbol V CC Tj T stg R thj-a mb DC Supply Voltage Junction Temperature St orage Temperature Range Thermal Resistance Junction-ambient RF+, RF- RF Input Parameter Value 5.9 8 150 -40 to 125 80
o
Uni t V dBm
o o
C C
C/W
2/10
STB5600
PIN CONFIGURATION Apply 5V at the CE, VCCRF, VCCIF, VCCLOGIC pins, apply 3 V at the VCCDRIV E
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Symbol IF1+ IF 1V CCRF RF+ RF V CCRF V EERF GNDRF V CCRF LO+ LO V CCRF V CCLOGI C 80 MHz+ 80 MHzV CCLOGI C V EELOGIC CLOCK+ Not Connected GND DRIVE DATA GND DRIVE VCCDRIVE CE G ND GND LOGIC GND IF V EEIF V CCI F IF 2IF2+ V CCI F 0V 0.3 V or 3 V 0V 3V 3V 0V 0V 0V 2V 5V 4V 4V 5V CMO S Drive Ground 4 MHz Data CMOS Output CMO S Drive Ground CMO S Drive Power Supply Chip Enable Substrate Ground Logic G round IF Ground IF Voltage Reference IF Power Supply Limiting Amplifier Input Limiting Amplifier Input IF Power Supply 100 nF to VCCIF 100 nF to VEEIF see application circuit see application circuit 100 nF to VEEIF 7 pF to G ND DRIVE Typ. DC Bias 3.6 V 3.6 V 5V 3.5 V 3.5 V 5V 2V 0V 5V 3.5 V 3.5 V 5V 5V 4V 4V 5V 2V 0.3 V or 3 V Dexription Mixer O utput 1 Mixer O utput 2 RF Power Supply RF Input RF Input RF Power Supply RF Voltage Reference RF Ground RF Power Supply Local Oscillator Input Local Oscillator Input RF Power Supply Logic Power Supply 80 MHz Clock Input 80 MHz Clock Input Logic Power Supply Logic Voltage Reference 16 MHz Clock CMOS Output 100 nF to VEERF AC Coupled AC Coupled 100 nF to VEERF 100 nF to VEELOGIC AC Coupled AC Coupled 100 nF to VEELOGIC 100 nF to VCCLOG IC 7 pF to G ND DRIVE Extern al circuit see application circuit see application circuit 100 nF to V EERF AC Coupled AC Coupled 100 nF to VEERF 100 nF to VCCRF
3/10
STB5600
ELECTRICAL SPECIFICATION (VVCCRF = 3.3 V ...5.9 V; VVCCIF = 3.3 V ...5.9 V; VVCC LOGIC = 3.3 V ...5.9 V VVCCDRIVE = 3 V; Ta = 25 oC unless otherwise specified) LNA MIXER
Symb ol I VCCRF Z in Z out GC IIP1 NF f RF f IF Parameter Supply Current Differential Input Impedance Differential Output Impedance Voltage Conversion Gain Input Compression Point (1dB) Noise figure Input Signal Frequency (L1) Output Signal Frequency VVCCRF = 5 V @ 1575 MHz AC Coupled at RF+ RF - inputs @ 20 MHz AC Coupled at IF1+ IF1outputs R L > 3K, PI N = -80 dBm (V in = 75 Vp on 300 ) (see application circuit) 35 -60 5 1575 20 Note Min. 20 300 1 70 3 Typ . Max. 25 Un it mA pF pF dB dBm dB MHz MHz
LO INPUT BUFFER
Symb ol Z in Parameter Differential Input Impedance Input Signal Level Note @ 1555 MHz AC Coupled at LO+ LO - inputs -60 Min. Typ . 300 1 -40 -20 Max. Un it pF dBm
LIMITING AMPLIFIER
Symb ol I VCCIF Z in B Sens V I NMAX Parameter Supply Current Differential Input Impedance Bandwidth 3dB Limiter sensitivity Maximum Input Signal Input Signal @ 20 MHz AC Coupled Input Signal @ 20 MHz AC Coupled VVCCIF = 5 V @ 20 MHz AC Coupled at IF2+ IF2inputs 5 100 0.5 Note Min. 2.5 15 80 Typ . Max. 3.5 Un it mA K MHz Vp Vp
CLOCK INPUT BUFFER
Symb ol I VCCLOGIC Z in Parameter Supply Current Differential Input Impedance Input Signal Level N Division Ratio Note VVCC LOGIC = 5 V @ 80 MHz AC Coupled at 8O MHz+ 80 MHz- inputs @ 80 MHz AC Coupled at 8O MHz+ 80 MHz- inputs 5 5 Min. 5 8 2 100 Typ . Max. 7 Un it mA K pF mVp
4/10
STB5600
ELECTRICAL CHARACTERISTICS (Continued) OUTPUT SECTION
Symb ol I VCCDRI VE V OH V OL tr tf Parameter Supply Current High output voltage Low output voltage Rise Time Fall T ime V VCCDRI VE = 3 V Vp = VVCCDRIVE = 3 V Vn = GNDDRIVE C LOAD = 7 pF C LOAD = 7 pF Vp-0.4 Vn 6 2 Note Min. Typ . 8 Vp Vn+0.4 Max. Unit mA V V ns ns
APPLICATION CIRCUIT A typical application circuit is shown in figure 1. The RF input from the antenna downlead is fed via a ceramic filter and matching circuit to the RF+,RF- pins. The external LNA in the antenna should have between 10 and 35dB of amplifier gain, so the noise measured in a one MHz bandwidth should be -114dBm for kTB in 1 MHz + 2dB LNA noise figure +10/35 dB LNA gain (net) Total -102/ 77dBm at connector. Allowing 2dB for filter loss, -104/-79 is available at the matching circuit.
Fig. 1 Typical Application Circuit
5/10
STB5600
A.1 Matching Network The matching circuit may be a 50 Ohm / 300 Ohm balun transformer (figure 2), but a more economical solution is a tuned match as shown below. A single 10nH inductor is optimal in cost, but may not meet the users tolerance requirements over spreads of silicon and pcb material, as it has only around 1pF tuning capacitance ( 2pF in series with 2pF inside the package). Fig. 2 Matching Network with Balun
The first example (figure 3) increases the capacitance with a discrete capacitor, and uses a lower inductance value. Both examples assume that the ceramic filter is dc blocking, both input to output, and output to ground. Fig. 3 Matching Network with two elements
The second (figure 4) example allows optimum matching by rationing the capacitors appropriately to achieve voltage gain commensurate with the impedance translation. While it has a higher component count, it is the version most tolerant of component variations and board capacitance.
6/10
STB5600
Fig. 4 Matching Network with four elements
A.2 IF Filter The recommended IF filter is shown in figure 5. The stop band of the filter is to reject the alias images around 12MHz, and around 28MHz, where it should have at least 15dBc rejection. Note that the mixer output is low impedance, (70 Ohms), and the IF input is high impedance (15kOhms), so considerable voltage gain is achieved in the impedance matching filter. The filter also sets the bandwidth of the receiver, using the load impedance with the L/C ratio to set the filter Q. If desired, an external resistor may be added in parallel to reduce the Q. Note that the bandwidth must be much wider than the 2MHz needed to pass the power of the GPS signal... it must maintain linear phase across the 2MHz, even at the extremes of component tolerance.
Fig. 5 IF Filter
7/10
STB5600
A.3 Reference Oscillator The recommended dual output oscillator shown in figure 6 generates both the 81.84MHz signal that is divided down for the CPU 16.368MHz clock, but also the low amplitude 1555MHz first local oscillator signal . Note that some 2 volts of the 82MHz signal is available, and the capacitive tap on the tank circuit is used to reduce the amplitude to prevent excessive radiation. Note that the transistor must be a high frequency type, Ft of 8 GHz or greater, and that the collector inductor must have a self resonant frequency of 2.5GHz or higher.
Fig. 6 Reference Oscillator
8/10
STB5600
TQFP32 MECHANICAL DATA
DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.45 0.05 1.35 0.30 0.09 9.00 7.00 5.60 0.80 9.00 7.00 5.60 0.60 1.00 0o(min.), 7o (max.) 0.75 0.018 1.40 0.37 mm TYP. MAX. 1.60 0.15 1.45 0.45 0.20 0.002 0.053 0.012 0.004 0.354 0.276 0.220 0.031 0.354 0.276 0.220 0.024 0.039 0.030 0.055 0.015 MIN. inch TYP. MAX. 0.063 0.006 0.057 0.018 0.008
D D1 D3 A1
17 16
0.10mm .004 Seating Plane
A A2
24 25
E3
E1
B
E
32 1 8
9
B C L K
e L1
TQFP32
0060661
9/10
STB5600
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1998 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. .
10/10

▲Up To Search▲

Price & Availability of STB5600

	To Download STB5600 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .